clang-ias.patch (6168B)
1 diff --git a/nss/lib/freebl/Makefile b/nss/lib/freebl/Makefile 2 index 7673357..1d2fe12 100644 3 --- a/nss/lib/freebl/Makefile 4 +++ b/nss/lib/freebl/Makefile 5 @@ -746,15 +746,6 @@ ifdef INTEL_GCM 6 # GCM binary needs -mssse3 7 # 8 $(OBJDIR)/$(PROG_PREFIX)intel-gcm-wrap$(OBJ_SUFFIX): CFLAGS += -mssse3 9 - 10 -# The integrated assembler in Clang 3.2 does not support % in the 11 -# expression of a .set directive. intel-gcm.s uses .set to give 12 -# symbolic names to registers, for example, 13 -# .set Htbl, %rdi 14 -# So we can't use Clang's integrated assembler with intel-gcm.s. 15 -ifdef CC_IS_CLANG 16 -$(OBJDIR)/$(PROG_PREFIX)intel-gcm$(OBJ_SUFFIX): CFLAGS += -no-integrated-as 17 -endif 18 endif 19 20 ifdef INTEL_GCM_CLANG_CL 21 diff --git a/nss/lib/freebl/ppc-gcm.s b/nss/lib/freebl/ppc-gcm.s 22 index 06ad586..471c502 100644 23 --- a/nss/lib/freebl/ppc-gcm.s 24 +++ b/nss/lib/freebl/ppc-gcm.s 25 @@ -4,9 +4,6 @@ 26 27 # Registers: 28 29 -.set SP, 1 30 -.set TOCP, 2 31 - 32 .macro VEC_LOAD_DATA VR, DATA, GPR 33 addis \GPR, 2, \DATA@got@ha 34 ld \GPR, \DATA@got@l(\GPR) 35 @@ -90,8 +87,8 @@ 36 .type ppc_aes_gcmINIT,@function 37 .align 5 38 ppc_aes_gcmINIT: 39 -addis TOCP,12,(.TOC.-ppc_aes_gcmINIT)@ha 40 -addi TOCP,TOCP,(.TOC.-ppc_aes_gcmINIT)@l 41 +addis %r2,12,(.TOC.-ppc_aes_gcmINIT)@ha 42 +addi %r2,%r2,(.TOC.-ppc_aes_gcmINIT)@l 43 .localentry ppc_aes_gcmINIT, .-ppc_aes_gcmINIT 44 45 .set Htbl, 3 46 @@ -255,8 +252,8 @@ addi TOCP,TOCP,(.TOC.-ppc_aes_gcmINIT)@l 47 .type ppc_aes_gcmHASH,@function 48 .align 5 49 ppc_aes_gcmHASH: 50 -addis TOCP,12,(.TOC.-ppc_aes_gcmHASH)@ha 51 -addi TOCP,TOCP,(.TOC.-ppc_aes_gcmHASH)@l 52 +addis %r2,12,(.TOC.-ppc_aes_gcmHASH)@ha 53 +addi %r2,%r2,(.TOC.-ppc_aes_gcmHASH)@l 54 .localentry ppc_aes_gcmHASH, .-ppc_aes_gcmHASH 55 56 .set Htbl, 3 57 @@ -290,13 +287,13 @@ addi TOCP,TOCP,(.TOC.-ppc_aes_gcmHASH)@l 58 .set H4L, 31 59 60 # store non-volatile vector registers 61 - addi 7, SP, -16 62 + addi 7, %r1, -16 63 stvx 31, 0, 7 64 - addi 7, SP, -32 65 + addi 7, %r1, -32 66 stvx 30, 0, 7 67 - addi 7, SP, -48 68 + addi 7, %r1, -48 69 stvx 29, 0, 7 70 - addi 7, SP, -64 71 + addi 7, %r1, -64 72 stvx 28, 0, 7 73 74 VEC_LOAD_DATA SWAP_MASK, .Ldb_bswap_mask, 7 75 @@ -482,13 +479,13 @@ addi TOCP,TOCP,(.TOC.-ppc_aes_gcmHASH)@l 76 VEC_STORE D, Tp, 0 77 78 # restore non-volatile vector registers 79 - addi 7, SP, -16 80 + addi 7, %r1, -16 81 lvx 31, 0, 7 82 - addi 7, SP, -32 83 + addi 7, %r1, -32 84 lvx 30, 0, 7 85 - addi 7, SP, -48 86 + addi 7, %r1, -48 87 lvx 29, 0, 7 88 - addi 7, SP, -64 89 + addi 7, %r1, -64 90 lvx 28, 0, 7 91 blr 92 .size ppc_aes_gcmHASH, . - ppc_aes_gcmHASH 93 @@ -500,8 +497,8 @@ addi TOCP,TOCP,(.TOC.-ppc_aes_gcmHASH)@l 94 .type ppc_aes_gcmTAG,@function 95 .align 5 96 ppc_aes_gcmTAG: 97 -addis TOCP,12,(.TOC.-ppc_aes_gcmTAG)@ha 98 -addi TOCP,TOCP,(.TOC.-ppc_aes_gcmTAG)@l 99 +addis %r2,12,(.TOC.-ppc_aes_gcmTAG)@ha 100 +addi %r2,%r2,(.TOC.-ppc_aes_gcmTAG)@l 101 .localentry ppc_aes_gcmTAG, .-ppc_aes_gcmTAG 102 103 .set Htbl, 3 104 @@ -567,8 +564,8 @@ addi TOCP,TOCP,(.TOC.-ppc_aes_gcmTAG)@l 105 .type ppc_aes_gcmCRYPT,@function 106 .align 5 107 ppc_aes_gcmCRYPT: 108 -addis TOCP,12,(.TOC.-ppc_aes_gcmCRYPT)@ha 109 -addi TOCP,TOCP,(.TOC.-ppc_aes_gcmCRYPT)@l 110 +addis %r2,12,(.TOC.-ppc_aes_gcmCRYPT)@ha 111 +addi %r2,%r2,(.TOC.-ppc_aes_gcmCRYPT)@l 112 .localentry ppc_aes_gcmCRYPT, .-ppc_aes_gcmCRYPT 113 114 .set PT, 3 115 @@ -639,30 +636,30 @@ addi TOCP,TOCP,(.TOC.-ppc_aes_gcmCRYPT)@l 116 .endm 117 118 # store non-volatile general registers 119 - std 31,-8(SP); 120 - std 30,-16(SP); 121 - std 29,-24(SP); 122 - std 28,-32(SP); 123 - std 27,-40(SP); 124 - std 26,-48(SP); 125 - std 25,-56(SP); 126 + std 31,-8(%r1); 127 + std 30,-16(%r1); 128 + std 29,-24(%r1); 129 + std 28,-32(%r1); 130 + std 27,-40(%r1); 131 + std 26,-48(%r1); 132 + std 25,-56(%r1); 133 134 # store non-volatile vector registers 135 - addi 9, SP, -80 136 + addi 9, %r1, -80 137 stvx 31, 0, 9 138 - addi 9, SP, -96 139 + addi 9, %r1, -96 140 stvx 30, 0, 9 141 - addi 9, SP, -112 142 + addi 9, %r1, -112 143 stvx 29, 0, 9 144 - addi 9, SP, -128 145 + addi 9, %r1, -128 146 stvx 28, 0, 9 147 - addi 9, SP, -144 148 + addi 9, %r1, -144 149 stvx 27, 0, 9 150 - addi 9, SP, -160 151 + addi 9, %r1, -160 152 stvx 26, 0, 9 153 - addi 9, SP, -176 154 + addi 9, %r1, -176 155 stvx 25, 0, 9 156 - addi 9, SP, -192 157 + addi 9, %r1, -192 158 stvx 24, 0, 9 159 160 VEC_LOAD_DATA SWAP_MASK, .Ldb_bswap_mask, 9 161 @@ -1013,31 +1010,31 @@ addi TOCP,TOCP,(.TOC.-ppc_aes_gcmCRYPT)@l 162 VEC_STORE CTR, CTRP, 0 163 164 # restore non-volatile vector registers 165 - addi 9, SP, -80 166 + addi 9, %r1, -80 167 lvx 31, 0, 9 168 - addi 9, SP, -96 169 + addi 9, %r1, -96 170 lvx 30, 0, 9 171 - addi 9, SP, -112 172 + addi 9, %r1, -112 173 lvx 29, 0, 9 174 - addi 9, SP, -128 175 + addi 9, %r1, -128 176 lvx 28, 0, 9 177 - addi 9, SP, -144 178 + addi 9, %r1, -144 179 lvx 27, 0, 9 180 - addi 9, SP, -160 181 + addi 9, %r1, -160 182 lvx 26, 0, 9 183 - addi 9, SP, -176 184 + addi 9, %r1, -176 185 lvx 25, 0, 9 186 - addi 9, SP, -192 187 + addi 9, %r1, -192 188 lvx 24, 0, 9 189 190 # restore non-volatile general registers 191 - ld 31,-8(SP); 192 - ld 30,-16(SP); 193 - ld 29,-24(SP); 194 - ld 28,-32(SP); 195 - ld 27,-40(SP); 196 - ld 26,-48(SP); 197 - ld 25,-56(SP); 198 + ld 31,-8(%r1); 199 + ld 30,-16(%r1); 200 + ld 29,-24(%r1); 201 + ld 28,-32(%r1); 202 + ld 27,-40(%r1); 203 + ld 26,-48(%r1); 204 + ld 25,-56(%r1); 205 blr 206 .size ppc_aes_gcmCRYPT, . - ppc_aes_gcmCRYPT 207